Verification Engineer, SystemVerilog/UVM

Hi All,

Requirement Name: DV Profiles ( 4 to 7 Years)

Skill: Verification

Job Description: Candidate must have good understanding of the System-Verilog, UVM and Test case development. Must have good debugging skills Required experience in Cadence Tool chain (Xcellium) Experience in AMBA protocol (AXI3/4, AHB, APB)Experience in usage of 3rd party VIP is plus Experience in PCIe protocol is plus

Please share your profile to [email protected]

Regards,

Jaya