Staff IP Design Engineer

Job Overview

We are seeking a Staff IP Design Engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The candidate will work closely with an architect to translate specifications into high-speed RTL design, focusing on performance, power, and logic utilization.

Responsibilities

• Translate specifications into high-speed RTL designs.
• Perform logic verification, debug, and timing closure.
• Package soft IP, develop example designs and testbenches.
• Work with team to drive project completion and provide technical guidance.

Qualifications

• 8+ years FPGA or system design experience; BS/MS/PhD in Electronics or Computer Engineering required.
• Experience in high-speed SERDES protocols (PCIe, Ethernet, CPRI, JESD204B/C) or peripherals (SPI, I2C, I3C).
• Hands-on FPGA RTL design, logic verification, debug, timing closure.
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