Vacancy Description
Job Description
Job Responsibilities
Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must. Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug. Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits. Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency. Generate Verification Plan from the Specifications using vManager Determine Coverage and design completeness requirements Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic reporting Set-up and run regression reports Works diligently to accomplish pr...
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