Soc/Ip Design Verification Engineer (Guadalajara)

Job Details
We're looking for a hands‐on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained‐random), coverage closure, and debug across block, subsystem, and SoC levels. You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high‐quality silicon on schedule.
Key Responsibilities
Own the verification lifecycle for one or more IPs/subsystems/SoC top‐level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models) with scalable, reusable components.
Develop test content: constrained‐random sequences, scenario tests, stimulus libraries, checkers, and assertions.
Debug failures quickly and methodically across simulation and emulati...