Soc verification lead

Lead Design Verification Engineer
Experience: 10+ Years
Location: Bangalore
Job Description:
We are looking for an experienced Design Verification Engineer with strong expertise in IP/Sub-system/So C level verification and high-speed protocols . The candidate will be responsible for driving end-to-end verification activities, defining verification strategies, and leading complex verification closures.
Key Responsibilities:
Define and execute verification plans and methodologies for IP and So C level designs.
Develop scalable UVM/System Verilog based verification environments from scratch.
Lead testbench architecture, stimulus creation, scoreboards, assertions, and functional coverage .
Drive verification closure including coverage analysis, regressions, and sign-off metrics.
Work closely with design, architecture, and firmware teams for feature validation and debug.
Handle complex debug at RTL, gate level, and emulation/prototyping platforms .
Mentor...