Senior Role:
We are seeking a skilled Senior Engineer to join our team and contribute to the design and development of our advanced semiconductor products. As a Senior Engineer, you will be responsible for the following:
Implementing off-chip memory built-in self-test (MBIST) and scan design techniques to enhance the testability and fault coverage of our designs. Providing and maintaining Logical Equivalence Checking (LEC) and Synopsys Design Constraints (SDC) scripts for Formal Verification and Timing Constraint Check processes. Collaborating with Test Engineers to analyze and understand Design-for-Testability (DFT) requirements and providing efficient solutions for DFT testing.
Requirements for Senior Role:
A Bachelor's or Master's degree in Electrical Engineering or a related engineering field. Proficiency in programming skills and UNIX shell scripting. Familiarity with Verilog and Register Transfer Level (...