Senior PCIe IP RTL Engineer — Design & Verification

Bitdeer Group in Singapore is looking for an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe-related IP blocks. This role involves ensuring functional coverage, contributing to both pre-silicon and post-silicon debug activities, and collaborating with various teams to deliver high-quality IP solutions.

The ideal candidate will have at least 5 years of experience in semiconductor R&D, a strong understanding of PCIe architecture, and the ability to work with scripting languages like Perl and Shell.