Vacancy Description
Senior Packaging Design Engineer, Silicon
_corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
_info_outline_
XNote: By applying to this position you will have an opportunity to share your preferred working location from the following: **Mountain View, CA, USA; San Diego, CA, USA** .
**Minimum qualifications:**
+ Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
+ 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs.
+ Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production.
+ Experienc...
_corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
_info_outline_
XNote: By applying to this position you will have an opportunity to share your preferred working location from the following: **Mountain View, CA, USA; San Diego, CA, USA** .
**Minimum qualifications:**
+ Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
+ 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs.
+ Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production.
+ Experienc...
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