Senior FPGA IP Design Engineer — High-Speed SerDes & Video

Lattice Malaysia is seeking a Senior IP Design Engineer to develop connectivity IP portfolios for our FPGA products. This role involves close collaboration with architects to turn specifications into high-speed RTL designs while ensuring optimal performance, power efficiency, and logic utilization.

The ideal candidate will have a strong background in FPGA design and programming skills in C/C++, Perl, TCL, or Python, along with a minimum of 5 years of relevant experience.

Competitive compensation and benefits aligned with industry standards.