Senior Engineer, STPG PE (FDV-Verilog)

Senior Engineer – Product Engineering, NAND Validation/Characterization (Senior Engineer in Product Engineering, NAND Validation/Characterization, focusing on functional and design validation).

The role builds scalable, reusable, and automated test program frameworks, including AI/ML‑driven initiatives, to support deterministic and pseudo‑random validation flows. Responsibilities include design of Verilog test programs, validation of NAND datasheet commands, features, interfaces, and customer‑mode operations on silicon platforms, and performing deep failure analysis and root‑cause identification.

• Designed and executed functional and design validation flows for advanced RG NAND devices using simulation platforms.
• Developed deterministic usage‑case tests and random sequence generators to validate NAND commands and customer‑mode features.
• Performed detailed failure analysis of issues, root‑cause invest...