Senior Engineer, ASIC Development Engineering (STA, Sign Off)

Position Overview:

We are seeking a highly skilled and experienced Senior Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a  team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a good  understanding of STA methodologies, prior experience of timing signoff  and a strategic vision to drive continuous improvement in our timing analysis processes.

Key Responsibilities:

- Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis.

- Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.

- Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seam...