Vacancy Description
Experience: 6+ Yrs
Skill: IP Verification
We are looking for an experienced Design Verification Engineer with strong expertise in PCIe IP verification , SystemVerilog , and UVM .
Hands-on experience in PCIe protocol, VIP, coverage-driven verification & debugging
Strong skills in SV/UVM testbench development, assertions, and scoreboarding
Experience in IP/Sub-system level verification, test plan creation & reviews
Solid understanding of verification flows, regressions, and scripting (Python/Perl preferred)
Excellent problem-solving and ability to work with cross-functional teams
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