Senior ASIC RTL Front-End Engineer

Bitdeer Technologies Group in Penang is seeking an experienced RTL design engineer to contribute to ASIC projects and collaborate across design, verification, and implementation teams. The role focuses on robust RTL development and integration of IP for high‑efficiency mining and AI workloads in a startup‑style environment.

The candidate should have 3–5+ years of RTL experience, strong knowledge of computer architecture and VLSI design, and hands‑on work on GPGPU/CPU modules, memory subsystems,