Principal Layout Engineer

Job Description

• A layout technical expert taking chip top ownership of analog‑on‑top ASIC developments.
• Hands‑on technical contributor, able to take chip top ownership including tape‑out procedures.
• Hands‑on in analog/mixed‑signal layout methodologies, high‑voltage design practices, and power IC architectures.
• A team player, able to collaborate with a global layout team and cross‑discipline stakeholders.
• Gets drive & motivation from successfully taping out chips with the high quality layout.
• Guide junior layout engineers, review their work, and enforce best practices.

Required experience

• 10+ years of experience
• Experience with nodes in the range of 40nm to 180nm is a must.
• Experience with BCD technologies is a must. Experience with HV CMOS is a plus.
• Strong knowledge of power management ICs and high‑voltage layout constraints.
• Experience with isolation techno...