Physical Low Power Validation Engineer

Physical Low Power Validation Engineer

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 8 years of experience in post-layout physical netlist validation or low-power signoff in an ASIC design environment.
+ Experience in static low-power rule checking tools (e.g., VCLP or CLP) or debugging signal corruption or structural checks.
+ Experience debugging technical issues within the IEEE 1801 UPF framework or the physical gate-level netlist flow.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on comput...