Physical Design Lead – Place & Route (PnR) / Static Timing Analysis (STA)

Location: Bengaluru, India
Work Mode: Onsite
Experience: 8 15 Years
Industry: Semiconductor / VLSI / ASIC Design

We are seeking an experienced Physical Design Lead to drive the complete physical implementation flow for complex ASIC and SoC designs targeting advanced semiconductor technologies. The role involves leading Place & Route (PnR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification, Power Optimization, and Signoff while collaborating closely with RTL, DFT, Design Verification, Package, and Product Engineering teams.

The ideal candidate will have extensive experience delivering multiple successful tape-outs across advanced process nodes and possess strong leadership capabilit...