Physical Design Engineer: Floorplanning, P&R, DFT/STA

Alchip Technologies is seeking a Design Engineer to perform gate level netlist to GDS design tasks independently, focusing on floor planning, timing sign-off, and physical verification.

The ideal candidate should hold a Bachelor or MS degree in Electrical Engineering with solid knowledge of digital and analog electronics. Familiarity with Cadence EDI and Synopsys ICC design flow is important. A collaborative attitude to meet tape-out targets is also required.