PCIe Verification Architect

UST is seeking an experienced verification engineer to develop and execute PCIe IP/SoC verification plans and build SystemVerilog/UVM environments. You will create directed and constrained-random test cases to reach coverage goals and verify PCIe protocol (Gen3/Gen4/Gen5) for compliance and functional correctness.

In this role, you will debug RTL and simulation issues, analyze waveforms, and support verification closure while collaborating with design, architecture, and validation teams across