Vacancy Description
Job Description1. plan test plans and function pattern for MP
2. Test and Verify IC functionality, performance, power etc.
3. Analysis ATE test data, Clarify testing issue, yield improvement
4. AVS design for low power
#LI-YT1Requirement1. Familiar with Verilog/SystemVerilog
2. Familiar with IC design and MP flow
Good to have:
1. Familiar with Perl and Python
2. Familiar with low power methodology
2. Test and Verify IC functionality, performance, power etc.
3. Analysis ATE test data, Clarify testing issue, yield improvement
4. AVS design for low power
#LI-YT1Requirement1. Familiar with Verilog/SystemVerilog
2. Familiar with IC design and MP flow
Good to have:
1. Familiar with Perl and Python
2. Familiar with low power methodology
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