Lead PMIC & Power IC Layout Engineer - Tape-Out Expert

Cyient in Hyderabad is seeking an experienced layout technical expert to take chip top ownership of analog-on-top ASIC developments. The ideal candidate will have 10+ years of experience, with a strong focus on power management ICs and layout methodologies.

You will collaborate with a global layout team, guide junior engineers, and ensure high-quality tape-out procedures. The role offers opportunities to work on next-generation PMIC and improve layout practices.