Lead ASIC Physical Design: End-to-End Timing & Power

TalentCloud Group in Zürich is seeking a senior Lead ASIC Physical Design Engineer to own and scale the backend implementation, defining RTL-to-GDSII strategy and building the team that executes it.

You will drive Synthesis, floorplanning, P&R, timing closure, power optimization, UPF/CPF, and integration of SRAMs and hard IP, with a focus on end-to-end ownership and hands-on leadership across RTL, circuit, and layout groups.