Intern: Application Engineering - Formal Verification

Intern: Application Engineering – Formal Verification

Location: Belo Horizonte, Brazil.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Intern in the System Verification Group – Technical Field Operations (TFO‑SVG) to become an expert in Formal Verification methodologies.

Responsibilities

• Activities focused on the Formal Verification field, mentored by experienced colleague, and reporting to higher management.
• Provide technical support to customers and field personnel in RTL verification solutions focused on the Jasper tool.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Run customer test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.
• Author appl...