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Front End ASIC RTL/Logic Senior Design Engineer

Altera

, penang, malaysia, penang, Malaysia Full-time July 19, 2026
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Vacancy Description

Job Details:

Job Description:

  • Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.

  • Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.

  • Work on post Silicon debug/characterization support of the designs.

Qualifications:

  • BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience

  • Strong in communication, leadership, investigation, problem solving & analytical skill

  • Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments

  • Knowledge of ...

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