Formal Verification Engineer

Formal Verification Engineer- Targets High quality silicon with no functional bugs by performing high quality pre-silicon verification Tasks Develop Specman E and SystemVerilog UVM compliant verification environments Formal verification of IPs (e.g. DMA, NVM FSMs) Creation of verification plans and execution of coverage closure Provide relevant reports to show progress Run regressions / help set up automatic regressions and debug failures / drive debugging Run verification environments quality checks with Certitude and improve environment to reach ASIL-D level for verification environment Skillset Proven working experience within the semiconductor industry in constraint random functional and formal verification Expertise in hardware verification using SystemVerilog UVM Expertise in formal verification using Cadence JasperGold Knowledge of using regression and coverage analysis tools as well as knowledge of test bench qualification Working experience in international and cross-functiona...