Vacancy Description
Job Responsibilities:
- Responsible for Full-chip Physical Verification Sign-off in area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
- Co-work with Place & Route team to resolve full-chip layout integration issues.
- Coordinates with internal IP owners on IP related issues.
- Coordinates with Manufacturing Team on DRC related issues.
- Provide automation solutions to improve efficiency in tape-out flow.
- Report on tapeout PV issues.
- Bachelor/master’s degree in electrical/Electronic Engineering/Computer Science
- Familiar with IC Design front-to-backend flow
- Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
- Proficient in script programming, such as Python, TCL, Perl, or C-shell
- Proficient in UNIX (Linux) platforms
- Strong communication skills, problem solving and analytical skills.
- Experience with 3D IC design (e.g., CoWoS, SoIC, EMIB) ...
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