Design for Test (DFT)

This role is for one of the Weekday's clients

Salary range: Rs 700000 - Rs 1800000 (ie INR 7-18 LPA)

Experience: 4+ yrs

Location: Hyderabad

Job Type: full-time

We are seeking a highly skilled Design for Test (DFT) Engineer to drive the implementation, validation, and optimization of DFT methodologies across complex SoC designs. This role involves working on scan insertion, ATPG generation, MBIST, LBIST, and boundary scan implementation at both RTL and gate levels to ensure high test coverage, manufacturability, and silicon quality.

The ideal candidate will collaborate closely with design, verification, synthesis, STA, and validation teams to develop robust DFT architectures and ensure seamless integration across the chip development lifecycle. This position offers an opportunity to work on advanced semiconductor technologies while contributing to the successful delivery of high-performance SoCs.