Vacancy Description
About the Role:
We are seeking an experienced and highly technical Hardware Verification & Validation Engineer to drive the end-to-end testing of our cutting-edge ASIC designs. In this dynamic role, you will bridge the gap between pre-silicon verification and post-silicon lab validation. You will architect robust UVM testbenches for next-generation PCIe interfaces and lead hands-on silicon bring-up in the lab. If you have deep expertise in high-speed IO and thrive in cross-functional debugging environments, we want you on our team.
Key Responsibilities: Pre-Silicon Verification (PCIe Focus)
Verification Planning: Architect and execute comprehensive verification plans for PCIe Switch, Root Complex, and Endpoint configurations.
Testbench Development: Build and scale UVM-based environments from scratch to rigorously test complex PCIe protocol behaviors, including LTSSM transitions and link training.
Per...
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