Vacancy Description
Job Description1. Design and RTL implementation of SoC debug modules
2. Integration and verification of debug components (e.g., trace, monitor, access port)
3. Debug signal capture, trace, and analysis for SoC platforms
4. BUS topology and debug mechanism circuit design
5. Support SoC debug flow and issue localization
6. Collaborate with cross-functional teams to optimize debug performance
7. Documentation and test specification for SoC debug features
#LI-LL1Requirement1. Experience in RTL design (Verilog/SystemVerilog)
2. Familiarity with SoC architecture and debug methodologies
3. Knowledge of digital design verification and simulation tools
4. Good problem-solving and analytical skills
5. Strong teamwork and communication abilities
6. Experience with scripting languages (e.g., Python, Perl) is a plus
7. Experience with FPGA prototyping or lab debug is a plus
2. Integration and verification of debug components (e.g., trace, monitor, access port)
3. Debug signal capture, trace, and analysis for SoC platforms
4. BUS topology and debug mechanism circuit design
5. Support SoC debug flow and issue localization
6. Collaborate with cross-functional teams to optimize debug performance
7. Documentation and test specification for SoC debug features
#LI-LL1Requirement1. Experience in RTL design (Verilog/SystemVerilog)
2. Familiarity with SoC architecture and debug methodologies
3. Knowledge of digital design verification and simulation tools
4. Good problem-solving and analytical skills
5. Strong teamwork and communication abilities
6. Experience with scripting languages (e.g., Python, Perl) is a plus
7. Experience with FPGA prototyping or lab debug is a plus
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