Vacancy Description
Hi,
Title: Lead / Senior Verification engineer
Location: San Jose, CA / Santa Clara, CA
Duration: 6+ Months
Rate: $Open
Skills: UVM and System Verilog
Requirement:.
• 5+ or more years of proven experience on ASIC / SoC / IP Verification.
• Strong experience in SystemVerilog and UVM verification methodologies
• Proficiency in Object Oriented programming, computer architecture and data structures
• Strong analytical/problem solving skills and pronounced attention to details
• Strong interpersonal and communication skills
• Must be comfortable working across geographies
Note: If interested please send your updated resume and include your rate requirement along with your contact details with a suitable time when we can reach you. If you know of anyone in your sphere of contacts, who would be a perfect match for this job then, we would appreciate if you can forward this posting ...
Title: Lead / Senior Verification engineer
Location: San Jose, CA / Santa Clara, CA
Duration: 6+ Months
Rate: $Open
Skills: UVM and System Verilog
Requirement:.
• 5+ or more years of proven experience on ASIC / SoC / IP Verification.
• Strong experience in SystemVerilog and UVM verification methodologies
• Proficiency in Object Oriented programming, computer architecture and data structures
• Strong analytical/problem solving skills and pronounced attention to details
• Strong interpersonal and communication skills
• Must be comfortable working across geographies
Note: If interested please send your updated resume and include your rate requirement along with your contact details with a suitable time when we can reach you. If you know of anyone in your sphere of contacts, who would be a perfect match for this job then, we would appreciate if you can forward this posting ...
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