Vacancy Description
IP & SoC Verification Engineers
Experience : 5-15 years
Location : Bangalore
We are looking for professionals with 5–15 years of experience in Verilog, SystemVerilog, UVM, Constrained Random Verification, Functional Coverage, and SoC/IP verification.
Hands-on expertise in ARM/RISC-V based SoCs, Mixed Signal Verification, Formal Verification, AMS simulations, and Gate Level Simulations will be highly valued.
If you have strong debugging, root-cause analysis, and testbench/VIP development skills with a passion for complex SoC verification, we would love to connect with you.
Share your profile to:
[email protected]
⏳ Notice Period: 0–30 Days
Experience : 5-15 years
Location : Bangalore
We are looking for professionals with 5–15 years of experience in Verilog, SystemVerilog, UVM, Constrained Random Verification, Functional Coverage, and SoC/IP verification.
Hands-on expertise in ARM/RISC-V based SoCs, Mixed Signal Verification, Formal Verification, AMS simulations, and Gate Level Simulations will be highly valued.
If you have strong debugging, root-cause analysis, and testbench/VIP development skills with a passion for complex SoC verification, we would love to connect with you.
Share your profile to:
[email protected]
⏳ Notice Period: 0–30 Days
Ready to Apply?
अभी आवेदन करें
Submit your application for Senior Design Verification Engineer at ACL Digital
Apply for this Position