Vacancy Description
R&D Engineer – System‑On‑Chip ASIC Design
- Design and Physical Implementation of high-performance System‑On‑Chip ASICs.
- Leading a team in physical design implementation of large ASICs (500‑800 million gates).
- Providing technical support to customers and managing customer working relationships.
- Hands‑on competency using leading‑edge physical design EDA tools.
- In‑depth CPU/DSP architecture/algorithm knowledge and related physical design implementation knowledge.
- Collaborating with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.
- Utilizing commercial and in‑house EDA tools for the design and implementation of 500‑800 million gate integrated circuits in 5nm/3nm/2nm process technologies.
- Opportunity to participate in innovation, design flow, and methodology development to address challenges of designing into deep submicron processes and state‑of‑the‑art ...
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