Design Verification Engineer

Experience: 2-3 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities Verilog, System verilog, UVM VHDL, UVVM Simulator exposure with VCS, Questa, Xcelium Proficient in simulation and HW languages Should be able to interpret various LRMs and comply with semantics and testcase creation. Share the profiles to