Design Engineer

ASIC/DFT Engineers Experience : 3-4 years location : Chennai Experience in simulation and silicon validation. Strong expertise in DFT concepts, pattern simulation, silicon debug, and yield enhancement is required. Hands-on experience in ATPG (coverage analysis) and memory verification, repair, and failure root-cause analysis is essential. Experience with tools like TestKompress (ATPG), Mentor ETVerify (MBIST), and simulation tools such as VCS/ModelSim is preferred. Scripting knowledge in Perl/Shell is a plus along with adaptability to new tools and methodologies. Looking for candidates who can thrive in dynamic, global teams and handle multiple high-priority projects. Apply now: | Notice Period: 0–15 days | Location: Chennai