Chip Timing Optimization Engineer

Role: STA Engineer

Job Description

Key Responsibilities:

• Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions).
• Perform block‑level and full‑chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios.
• Own RTL synthesis (Design Compiler/Fusion Compiler/Genus), including constraint setup, QoR optimization, and netlist quality checks.
• Analyze timing violations, identify root causes, and collaborate with RTL, PD, and architecture teams to resolve issues.
• Validate constraints across synthesis, PnR, and sign‑off stages to ensure correctness and consistency.
• Drive timing ECOs and support post‑route optimization to achieve sign‑off timing.
• Generate timing reports, summarize key risks, and propose optimization strategies.
• Mentor junior engineers on STA, SDC, and synthesis best practices.

Req...