Architect - Asic Verification

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers, VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging com...