Analog Layout Engineer

Analog Layout Engineer Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field. 4 years of experience in analog layout design with a focus on TSMC 7nm , 5nm , and 3nm process technologies. Proficiency with Cadence Virtuoso , Mentor Graphics , Synopsys IC Compiler , or equivalent analog layout tools. Hands-on experience with TSMC PDKs and process technologies for 7nm , 5nm , and 3nm nodes. Strong knowledge of analog circuit design principles , including transistor-level design , biasing , signal integrity , and noise analysis . Extensive experience with DRC , LVS , parasitic extraction , and layout verification using tools such as Calibre and ICValidator . In-depth knowledge of FinFET , SOI , and other advanced semiconductor process technologies at sub-7nm nodes. Ability to optimize analog layouts for PPA (performance, power, area) . Experience with low-power design techniques in advanced process nodes . Familiarity wi...